module tb_nofif();


reg clk;
reg rst_n;
always	#5	clk = ~clk;
reg [7: 0] data_in;


always #15
	begin
		if (o_input_ready)
			begin
				data_in = data_in + 1'b1;
			end
		else
			data_in = data_in;
	end


wire o_input_ready2, o_output_valid;
wire [7: 0] o_data, o_data1;
wire o_accept1, o_accept2;
wire o_transmit1, o_transmit2;
reg i_output_ready;

initial
	begin
		clk = 1'b1;
		data_in <= 0;
		rst_n <= 1'b0;
		i_output_ready <= 1'b0;

		#19
		 rst_n <= 1'b1;
		i_output_ready <= 1'b1;

		#100
		 i_output_ready <= 1'b0;

		#100
		 i_output_ready <= 1'b1;
		#90
		 i_output_ready <= 1'b0;
		#100
		 i_output_ready <= 1'b1;
	end



skid_buffer#(
               .width ( 8 )
           )u_skid_buffer1(
               .clk ( clk ),
               .rst_n ( rst_n ),
               .i_data ( data_in ),
               .i_input_valid ( 1'b1 ),
               .i_output_ready ( o_input_ready2 ),
               .o_data ( o_data1 ),
               .o_output_valid ( o_output_valid1 ),
               .o_input_ready ( o_input_ready ),
               .o_accept ( o_accept1 ),
               .o_transmit ( o_transmit1 )
           );

skid_buffer#(
               .width ( 8 )
           )u_skid_buffer2(
               .clk ( clk ),
               .rst_n ( rst_n ),
               .i_data ( o_data1 ),
               .i_input_valid ( o_output_valid1 ),
               .i_output_ready ( i_output_ready ),
               .o_data ( o_data ),
               .o_output_valid ( o_output_valid ),
               .o_input_ready ( o_input_ready2 ),
               .o_accept ( o_accept2 ),
               .o_transmit ( o_transmit2 )
           );


endmodule
